The subject application is related to subject matter disclosed in the Japanese Patent Application No. Hei 11-348055 filed in Dec. 7, 1999, in Japan, to which the subject application claims priority under the Paris Convention and the entire contents of which is incorporated by reference herein.
Also, the entire contents of U.S. patent application Ser. No. 09/268,688 filed on Dec. 7, 1999, in United States of America as assigned to the assignee of the subject application and the entire contents of U.S. patent application Ser. No. 09/299,857 filed on Apr. 26, 1999, in United States of America as assigned to the assignee of the subject application are incorporated by reference herein.
1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device, more particular to a Double Data Rate (DDR) synchronous semiconductor memory device, and more generally to a multiple data rate transmission semiconductor memory device.
2. Prior Art
In recent years, it is an important issue in the quest for faster semiconductor systems to increase the data transmission rate between a CPU and a semiconductor memory device. One high speed data transmission design is a design that supports the double data rate mode.
FIG. 1 is a block diagram showing a semiconductor memory device in accordance with a conventional technique supporting the double data rate mode. FIG. 3 is a schematic diagram showing waveforms of the respective signals appearing when data is read from the semiconductor memory device. When an address signal, as illustrated in FIG. 3(B), is input to an address decoder 12 through an address register 11, the address decoder 12 serves to decode the address signal and output a decoded address signal for selecting a row to a row selection circuit 13, and a decoded address signal for selecting a column to a column selection circuit 14. The row selection circuit 13 and the column selection circuit 14 serve to select two memory cells for one I/O terminal in accordance with the address signals as decoded. Two data items are read out from the two memory cells substantially at the same time and input to data input/output circuits 16 and 17 through the data bus (1) and the data bus (2).
A multiplexer 18 serves to select and output one of the data items as outputted from the data input/output circuits 16 and 17 in synchronism with the high and low levels of the clock signal as illustrated in FIG. 3(A).
Namely, in accordance with the double data rate mode, the data bus structure is designed, unlike a conventional semiconductor memory device, in a dual structure consisting of two equivalent buses inside of a semiconductor memory device in order to read out and write at the doubled speed. Furthermore, the data transmission rate is doubled by alternately reading out of or writing in to the semiconductor memory device through a data input/output unit in synchronism with the high and low levels of the clock signal.
FIG. 2 is a block diagram showing the output control unit of the semiconductor memory device supporting the double data rate mode. The signals on the data buses (1) and (2) of the dual structure are amplified substantially at the same time by means of a sense amplifier 161, for the signal on data bus (1), and a sense amplifier 163, for the signal on data bus (2), in synchronism with a sense amplifier enabling signal/SAE, as illustrated in FIG. 3(C), in order to transfer the amplified signals to the output register 162, for the signal on data bus (1), and the output register 164, for the signal on data bus (2). The data items latched by the output register 162 and the output register 164 are input to the multiplexer 18 which is controlled by the clock signal, as illustrated in FIG. 3(A), and alternately output to the I/O terminal in synchronism with the high and low levels of the clock signal.
In accordance with the conventional semiconductor memory device supporting the double data rate mode as described above, the number of the sense amplifiers activated by the sense amplifier enabling signal /SAE is doubled as compared with that of a semiconductor memory device operating in the normal mode. For example, in the case of 36 I/O terminals, 72 sense amplifiers are activated at the same time. Since a sense amplifier consumes considerable current for the purpose of amplifying a very small differential voltage, a number of the sense amplifiers tend to function as a problematic noise source when they are activated at the same time as described above. This kind of power source noise may cause of malfunction and tends to degrade the sensitivity of the sense amplifier itself, resulting in deterioration in the characteristics thereof. Namely, in accordance with the conventional semiconductor memory device supporting the double data rate mode, there is a problem that substantial noise is generated by simultaneously activating double the number of the sense amplifier as compared with that with the number of sense amplifiers activated during a conventional memory operation.
The present invention has been developed in order to solve the shortcomings as described heretofore. It is an object of the present invention to provide an improved semiconductor memory device having an output control unit, which makes possible a reduction in the noise level without compromising the reading speed.
In brief, the above and other objects and advantages of the present invention are provided by a new and improved synchronous semiconductor memory device comprising: a memory cell array consisting of a plurality of memory cells for storing data items; a row selection circuit for receiving a row address signal decoded by a row decoder and selecting one row of the memory cell array; a column selection circuit for receiving a column address signal decoded by a column decoder and selecting first and second columns of the memory cell array at the same time; first and second sense amplifiers for amplifying first and second data items which are selected by the row selection circuit and the column selection circuit and outputted to first and second data lines; and a selector element for sequentially outputting the first and second data items which are amplified by the first and second sense amplifiers in accordance with a time-interleaved manner, wherein the second sense amplifier is activated after the first sense amplifier is activated.
In a preferred embodiment, further improvement is provided by the semiconductor memory device further comprising a first data storage element for latching a first data item amplified by the first sense amplifier and a second data storage element for latching a second data item amplified by the second sense amplifier.
Also, in a preferred embodiment, the second sense amplifier is activated by an activation signal which is generated through a first delay circuit by imposing a delay time on the activation signal for activating the first sense amplifier.
In accordance with this configuration, it is possible to disperse the electric current peak time points and reduce the noise level without compromising the reading speed by deferring activation of the sense amplifier, which is one of the two sense amplifiers for sensing and amplifying data to be outputted, when the clock signal is pulled down while the other sense amplifier serves to sense and amplify data to be outputted when the clock signal is pulled up. Also, in the sense amplifier serving to sense and amplify data to be outputted when the clock signal is pulled up, the interval between the time point at which the address becomes ready and the time point at which the sense amplifier enabling signal is given is elongated, as compared with the case where the sense amplifier serves to sense and amplify data to be outputted when the clock signal is pulled up, resulting in a relatively large margin for sensing and therefore resulting in a noise proof structure.
Furthermore, in a preferred embodiment, the delay time xcex94t1 imposed by the first delay circuit is selected to satisfy 0xe2x89xa6xcex94t1xe2x89xa6Tcy/2 where Tcy is a cycle time of said semiconductor memory device.
Furthermore, in a preferred embodiment, the size of the transistors of the second sense amplifier is designed to be smaller than that of the transistors of the first sense amplifier. By this configuration, it is possible to reduce the power consumption and the area of the semiconductor chip as occupied.
In accordance with the configuration, it is possible to make the semiconductor memory device faster and to reduces the power dissipation by deferring activation of the sense amplifier provided for sensing and amplifying data to be outputted when the clock signal is pulled down with a delay time of about a half of the cycle time.
Furthermore, in a preferred embodiment, the semiconductor memory device further comprises a second delay circuit for deferring the operation of the second data storage element in order to latch the second data item after the first data storage element latches the first data item.
Furthermore, in a preferred embodiment, the delay time xcex94t2 imposed by the second delay circuit is selected to satisfy 0xe2x89xa6xcex94t1xe2x89xa6xcex94t2xe2x89xa6Tcy/2 where xcex94t1 is the delay time imposed by the first delay circuit and Tcy is a cycle time of the semiconductor memory device.
In accordance with the configuration, it is possible to make the semiconductor memory device faster and to reduce the power dissipation by deferring activation of the sense amplifier provided for sensing and amplifying data with a delay time of about a half of the cycle time.
Furthermore, in a preferred embodiment, the first data storage element is composed of a latch circuit which serves to latch for a preceding half period of the cycle time a data item which is obtained after a first control clock signal is pulled up. The second data storage element is composed of a latch circuit, which serves to latch through the cycle time a data item, which is obtained after a second control clock signal is pulled up.
Furthermore, in a preferred embodiment, the first data storage element is composed of a latch circuit which serves to latch for a preceding half period of cycle time a data item which is obtained after a control clock signal is pulled up. The second data storage element is composed of a latch circuit which serves to latch for a subsequent half period of the cycle time a data item which is obtained after the control clock signal is pulled down.
Furthermore, in a preferred embodiment, the delay time of the first delay circuit is about a half of the cycle time.
In accordance with the configuration, the sense amplifiers are designed to be capable of maintaining data for a time period of no shorter than one half of the machine cycle while deferring activation of the sense amplifier provided for sensing and amplifying data to be outputted when the clock signal is pulled down by one half of the machine cycle. As a result, it is possible to reduce the area of the semiconductor chip and to make the semiconductor memory device faster and to reduce the power dissipation.
Furthermore, in a preferred embodiment, the selector element serves to selectively output the first and second data items in synchronism with the rising edge and the falling edge of the system clock.
In accordance with another aspect of the present invention, a synchronous semiconductor memory device comprising: a memory cell array including a plurality of memory cells for storing data items; first and second sense amplifiers connected in parallel to one output terminal for amplifying the data items stored in the plurality of memory cells; a selector element for selectively outputting the data items as outputted from the first and second sense amplifiers; and a first delay circuit for displacing the time points at which the first and second sense amplifiers are activated from one another, the first and second sense amplifiers are controlled to be capable of maintaining output data for a time period no shorter than a half of the cycle time.
In accordance with a further aspect of the present invention, a synchronous semiconductor memory device comprising: a memory cell array including a plurality of memory cells for storing data items; a row selection circuit for receiving a row address signal decoded by a row decoder and selecting one row of the memory cell array; a column selection circuit for receiving a column address signal decoded by a column decoder and selecting a plurality of columns of the memory cell array at the same time; a plurality of sense amplifiers for amplifying a plurality of data items which are selected by the row selection circuit and the column selection circuit and outputted to a plurality of data lines; and a selector element for sequentially outputting the data items one after another which are amplified by means of the plurality of the amplifiers in a time-interleaved manner, wherein the plurality of the amplifiers are activated one after another.
In accordance with this configuration, it is also possible to disperse the electric current peak time points and reduce the noise level without compromising the reading speed by deferring activation of the sense amplifier which is one of the two sense amplifiers for sensing and amplifying data to be outputted when the clock signal is pulled down while the other sense amplifier serves to sense and amplify data to be outputted when the clock signal is pulled up. Also, in the sense amplifier serving to sense and amplify data to be outputted when the clock signal is pulled up, the interval between the time point at which the address becomes ready and the time point at which the sense amplifier enabling signal is given is elongated, as compared with the case where the sense amplifier serves to sense and amplify data to be outputted when the clock signal is pulled up, resulting in a relatively large margin for sensing and therefore resulting in a noise proof structure.